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  cystech electronics corp. spec. no. : c397v8 issued date : 2012.03.14 revised date : 2012.03.15 page no. : 1/9 MTN4410V8 cystek product specification n-channel enhancement mode power mosfet MTN4410V8 features ? single drive requirement ? low on-resistance ? pb-free lead plating package applications ? synchronous rectifier for dc/dc converters ? telecom secondary side rectification ? high end server/ work station symbol outline MTN4410V8 dfn3 3 pin 1 g gate d drain s source ordering information device package shipping marking MTN4410V8 dfn3 3 (pb-free lead plating package) 3000 pcs / tape & reel 4410
cystech electronics corp. spec. no. : c397v8 issued date : 2012.03.14 revised date : 2012.03.15 page no. : 2/9 MTN4410V8 cystek product specification absolute maximum ratings (ta=25 c) parameter symbol limits unit drain-source voltage v ds 30 v gate-source voltage v gs 20 v continuous drain current @v gs =10v, t a =25 c i d 12 a continuous drain current @v gs =10v, t a =70 c i d 9.6 a pulsed drain current i dm 50 *1 a w total power dissipation linear derating factor p d 2.5 0.02 w/ c thermal resistance, junction-to-ambient, max r th,j-a 50 c/w operating junction and storage temperature tj, tstg -55~+150 c note : *1 . pulse width limited by safe operating area characteristics (tj=25 c, unless otherwise specified) symbol min. typ. max. unit test conditions static bv dss 30 - - v v gs =0, i d =250 a ? bv dss / ? tj - 0.02 - v/ c reference to 25c, i d =1ma v gs(th) 1.0 1.6 3.0 v v ds = v gs , i d =250 a g fs - 20 - s v ds =10v, i d =10a i gss - - d 100 na v gs = d 20 i dss - - 1 a v ds =30v, v gs =0 i dss - - 25 a v ds =24v, v gs =0, tj=55 c *r ds(on) - 9 13.5 m  v gs =10v, i d =10a *r ds(on) - 14 20 m  v gs =4.5v, i d =6a dynamic *qg - 16 - *qgs - 3.8 - *qgd - 6.2 - nc i d =10a, v ds =15v, v gs =5v *t d(on) - 7.5 - *tr - 17 - *t d(off) - 36 - *t f - 15 - ns v ds =25v, i d =1a, v gs =5v, r g =3.3  , r d =25  ciss - 1119 - coss - 124 - crss - 105 - pf v gs =0v, v ds =15v, f=1mhz source-drain diode *v sd - - 1.3 v i s =2.3a, v gs =0v *i s - - 2.3 a v d =v g =0, v s =1.3v *i sm - - 50 a *pulse test : pulse width 300 s, duty cycle 2%
cystech electronics corp. spec. no. : c397v8 issued date : 2012.03.14 revised date : 2012.03.15 page no. : 3/9 MTN4410V8 cystek product specification typical characteristics typical output characteristics 0 20 40 60 80 100 012345 vds, drain-source voltage(v) i d , drain current (a) 7v,8v,9v,10v vgs=2v vgs=3v 4v 5v 6v brekdown voltage vs ambient temperature 30 32 34 36 38 40 -75 -50 -25 0 25 50 75 100 125 150 175 tj, junction temperature(c) bv dss , drain-source breakdown voltage (v) i d =250 a, v gs =0v static drain-source on-state resistance vs drain current 1 10 100 1000 0.01 0.1 1 10 100 i d , drain current(a) r ds(on) , static drain-source on-state resistance(m) v gs =3v v gs =2.5v v gs =10v v gs =4.5v reverse drain current vs source-drain voltage 0.2 0.4 0.6 0.8 1 1.2 024681 i dr , reverse drain current(a) v sd , source-drain voltage(v) 0 tj=25c tj=150c v gs =0v static drain-source on-state resistance vs gate-source voltage 0 20 40 60 80 100 120 140 160 180 200 024681 0 drain-source on-state resistance vs junction tempearture 0 5 10 15 20 25 30 -60 -20 20 60 100 140 180 tj, junction temperature(c) r ds(on) , static drain-source on-state resistance(m) v gs =4.5v, i d =6a v gs =10v, i d =10a v gs , gate-source voltage(v) r ds(on) , static drain-source on- state resistance(m) i d =10a i d =6a
cystech electronics corp. spec. no. : c397v8 issued date : 2012.03.14 revised date : 2012.03.15 page no. : 4/9 MTN4410V8 cystek product specification typical characteristics(cont.) capacitance vs drain-to-source voltage 10 100 1000 10000 0.1 1 10 100 v ds , drain-source voltage(v) capacitance---(pf) c oss ciss crss threshold voltage vs junction tempearture 0.8 1 1.2 1.4 1.6 1.8 2 2.2 -60 -20 20 60 100 140 tj, junction temperature(c) v gs(th) , threshold voltage(v) i d =250 a forward transfer admittance vs drain current 0.01 0.1 1 10 0.001 0.01 0.1 1 10 i d , drain current(a) g fs , forward transfer admittance(s) v ds =10v pulsed ta=25c gate charge characteristics 0 2 4 6 8 10 0 5 10 15 20 25 30 35 40 qg, total gate charge(nc) v gs , gate-source voltage(v) i d =10a v ds =5v v ds =10v v ds =15v maximum safe operating area 0.01 0.1 1 10 100 0.01 0.1 1 10 100 v ds , drain-source voltage(v) i d , drain current(a) t a =25c, tj=150c v gs =10v, ja =50c/w single pulse dc 10ms 100ms r dson limited 10 s 1ms 100 s maximum drain current vs case temperature 0 5 10 15 20 25 30 25 50 75 100 125 150 175 t c , case temperature(c) i d , maximum drain current(a) v gs =10v
cystech electronics corp. spec. no. : c397v8 issued date : 2012.03.14 revised date : 2012.03.15 page no. : 5/9 MTN4410V8 cystek product specification typical characteristics(cont.) single pulse power rating, junction to ambient (note on page 2) 0 10 20 30 40 50 0.01 0.1 1 10 100 pulse width(s) power (w) t j(max) =150c t a =25c ja =50c/w transient thermal response curves 0.001 0.01 0.1 1 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 1.e+01 1.e+02 1.e+03 t 1 , square wave pulse duration(s) r(t), normalized effective transient thermal resistance single pulse 0.01 0.02 0.05 0.1 0.2 d=0.5 1.r ja (t)=r(t)*r ja 2.duty factor, d=t 1 /t 2 3.t jm -t a =p dm *r ja (t) 4.r ja =50c/w
cystech electronics corp. spec. no. : c397v8 issued date : 2012.03.14 revised date : 2012.03.15 page no. : 6/9 MTN4410V8 cystek product specification recommended soldering footprint unit : mm
cystech electronics corp. spec. no. : c397v8 issued date : 2012.03.14 revised date : 2012.03.15 page no. : 7/9 MTN4410V8 cystek product specification reel dimension carrier tape dimension
cystech electronics corp. spec. no. : c397v8 issued date : 2012.03.14 revised date : 2012.03.15 page no. : 8/9 MTN4410V8 cystek product specification recommended wave soldering condition product peak temperature soldering time pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) ? time(ts min to ts max ) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds time maintained above: ? temperature (t l ) ? time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak temperature(tp) 10-30 seconds 20-40 seconds ramp down rate 6 c/second max. 6c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of the package, measured on the package body surface.
cystech electronics corp. spec. no. : c397v8 issued date : 2012.03.14 revised date : 2012.03.15 page no. : 9/9 MTN4410V8 cystek product specification dfn3 3 dimension marking: date code s s s g d d d d 8-lead dfn3 3 plastic package cystek package code: v8 *: typical inches millimeters inches millimeters dim min. max. min. max. dim min. max. min. max. a 0.0276 0.0354 0.70 0.90 e 0.1181 0.1260 3.00 3.20 a1 0.0000 0.0197 0.00 0.50 e1 0.0531 0.0610 1.35 1.55 b 0.0094 0.0138 0.24 0.35 e 0.0256 bsc 0.65 bsc c 0.0039 0.0079 0.10 0.20 h 0.1260 0.1339 3.20 3.40 d 0.1280 0.1339 3.25 3.40 l 0.0118 0.0197 0.30 0.50 d1 0.1201 0.1280 3.05 3.25 l1 0.0039 0.0079 0.10 0.20 d2 0.0945 0.1024 2.40 2.60 l2 0.0445 ref 1.13 ref notes: 1.controlling dimension: millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing spec ification or packing method, please cont act your local cystek sales office. material: ? lead: pure tin plated. ? mold compound: epoxy resin family, flammability solid burning class: ul94v-0. important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitab le for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance .


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